· Growth method: CVD synthesis
· Chip dimensions: 10 mm x 10 mm
· Chip thickness: 675 μm
· Number of GFETs per chip: 36
· Gate oxide thickness: 90 nm
· Gate oxide material: SiO2
· Resistivity of substrate: 1-10 Ω.cm
· Metallization: Chromium/Gold 5/50nm
· Graphene field-effect mobility: >1000 cm2/V.s
· Dirac point: <50 V · Minimum working devices: >75 %”
Call for Price
GFET-S10 (Die size 10 mm x 10 mm) – Processed in Clean Room Class 1000
The GFET-S10 chip from Graphenea provides 36 graphene devices distributed in a grid pattern on the chip. Thirty devices have a Hall-bar geometry and six have a 2-probe geometry. The Hall-bar devices can be used for Hall-bar measurements as well as 4-probe and 2-probe devices. There are varying graphene channel dimensions to allow investigation of geometry dependence on device properties.
The new version replaces Ni/Al contacts by Cr/Au, which are more inert and stable.