Growth method: CVD synthesis
- Polymer assisted transfer
- Die dimensions: 4 mm x 4 mm
- Chip thickness: 525 μm
- Number of channels per chip: 28
- Gate Oxide thickness: 90 nm
- Gate Oxide material: SiO2
- Resistivity of substrate: 1-10 Ω·cm
- Metallization: Au contacts
- Encapsulation: 50 nm Al2O3
- Graphene field-effect mobility: >1000 cm2/V.s
- Dirac point (liquid gating in PBS): <1 V
- Yield: >75 %